Wishbone is an interconnect for Systems-on-Chip. It's been placed in the public domain and is (as far as we know) free from patents and royalties. Wishbone is widely used in free and open source designs, but it can also be used in commercial designs without limitations.
Today, the most used versions of Wishbone are revision B.3, and to a lesser extend, revision B.4. Revision B.4 most notably adds support for pipelining more efficient access to high-latency peripherals like DRAM.
Currently, the B3.1 specification is discussed. It is a minor revision to the B3 spec with clarifications. There will be a nother major specification process starting soon. You can contribute to the spec via our GitHub repository.
The primary author and maintainer of the Wishbone specification is Richard Herveille. The specification is now maintained by a group of people under the umbrella of the FOSSi Foundation. Please join the firstname.lastname@example.org mailing list (subscribe) if you have questions or want to contribute to the specification process.